Overview

We are seeking a highly experienced Architect specializing in high‑speed SerDes design with deep expertise in advanced analog/mixed‑signal circuits, XSR (Extra‑Short‑Reach) interfaces, and optical I/O technologies. In this role, you will provide technical leadership across complex, next‑generation PHY architectures, driving innovation from concept through production. You will work with cross‑functional teams and influence strategic direction across product lines while solving highly complex design challenges in advanced process nodes. Key Responsibilities

Lead the architectural definition of the E224+ SerDes, including identifying required modifications to meet customer‑driven performance, power, and latency targets. Architect and specify high‑performance analog front‑ends, including CTLE/DFE, TX FIR filters, PLLs/CDRs, ADC/DAC‑based architectures, and clocking subsystems. Updated channel modeling assumptions VSR‑specific equalization strategies AFE re‑partit...