Join Ciena as a Senior ASIC Engineer focusing on synthesis and static timing analysis. Make a significant impact on high-speed optical networking technologies. In this pivotal role at Ciena, you will work on the Wavelogic DSP programs, driving frontend implementation tasks such as synthesis and logical equivalence checking. You will ensure functional integrity through validating clock domains and collaborating with various engineering teams for seamless integration and comprehensive design validation. Responsibilities

Perform synthesis and clock domain validation for ASICs Create and optimize scripts improving workflows Maintain timing constraints essential for subsystem integration Validate designs across pre and post-layout stages Collaborate closely with IP development and EDA partners Qualifications

Degree in Electrical or Computer Engineering Solid experience in static timing analysis within ASIC environments Familiarity with ASIC implementation and RTL design Ab...