Our client is seeking a highly experienced ASIC Verification Engineer to help develop and verify complex digital ASICs in a collaborative, geographically diverse environment.

Key Responsibilities

Lead the development of verification infrastructure for advanced ASIC designs

Create System Verilog/UVM-based protocol and traffic generators/checkers

Develop and execute test plans based on functional and standards requirements

Define, develop, and run self-checking tests for complex digital ASICs

Required Qualifications

Bachelor’s degree in computer science or electrical engineering (master’s preferred)

8+ years of experience in ASIC verification

Proven experience in developing and implementing test plans at block or sub-chip levels

Proficiency in System Verilog and scripting languages such as Python

Deep understanding of UVM methodology

Experience with assertions, functional coverage,...