Take on a transformative role at Ciena as a Senior ASIC Engineer specializing in Digital Signal Processing. Your skills in synthesis and static timing will empower industry-leading ASIC designs.
As a pivotal member of Ciena’s engineering team, you will focus on frontend implementation and drive high-performance outcomes. This position demands expertise in static timing analysis and logical equivalence verification, alongside collaboration with diverse engineering disciplines to ensure project success.
Key Responsibilities:
• Oversee frontend implementation for assigned IPs
• Maintain timing constraints for integration signoff
• Validate logical equivalence through various stages
• Collaborate on ASIC integration and design activities
• Enhance automation with scripting tools
Requirements:
• B.Sc. in Electrical or Computer Engineering
• Experience in ASIC synthesis and timing analysis
• Strong understanding of ASIC design flows
• Proficient in hardwar...