Ciena seeks a Digital Verification Engineer to innovate verification processes in a leading telecommunications firm. Embrace a culture that prioritizes flexibility and a commitment to individual growth.

In this Senior Digital Verification Engineer role, you will validate crucial components of Ciena's Wavelogic modem technology. Your expertise in C++, System Verilog, UVM, and formal verification will guide effective validation of FEC functional blocks. Collaborate closely with multidisciplinary teams to simulate, analyze, and ensure performance standards while mentoring junior engineers for their professional development.

Key Responsibilities: • Analyze FEC architecture, collaborating with designers • Develop comprehensive verification strategies and tests • Validate architectural FEC blocks via simulation methods • Build testbench components using System Verilog UVM • Provide updates on verification status and potential risks

Requirements: • Minimum 10 years ...