3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking a DRAM Engineering Group Layout Designer to translate schematics into layout and develop methodologies for issue resolution. You will collaborate with design and other engineering teams to apply various layout techniques.

The ideal candidate will have over 4 years of experience with Cadence VLE/VXL and Calibre DRC/LVS, a Bachelor's degree in Electrical or related fields, and a strong electrical engineering background. Responsibilities include designing and verifying analog and digital layouts.