Advanced english Design, simulate, implement and test digital logic for FPGA using Verilog Perform synthesis, timing analysis, floorplanning and test using Xilinx Vivado and Synopsys HAPS tools. Write constraints to fix timing problems. Programming skills in TCL (for Vivado and open OCD) and python. Experience in board tests using JTAG probes for ARM cores, logic analyzer, serial ports, Vivado's ILA probes, etc. Experience in use AI in the daily tasks, tool flow improvement and project analysis. Experience in So C design or verification is a plus. Experience in Emulation (HAPS, Zebu, Palladium) is a plus.