Leverage your expertise as an Expert PLL Architect and Design Engineer in cutting-edge PLL technologies. Lead designs and simulations while optimizing advanced node processes and PLL systems.
We seek a professional with a Master’s degree or PhD in Electrical Engineering and a minimum of 5 years in PLL design experience. The successful candidate will utilize Cadence Virtuoso for transistor-level simulations while addressing challenges like voltage-controlled oscillator optimization. You will perform PLL integrations in advanced applications, ensuring system-level performance.
Key Responsibilities:
• Design and simulate PLL components using Cadence Virtuoso
• Perform lab characterization and PLL bring-up
• Conduct comprehensive validation for system-level integration
• Supervise layout verification and optimization
• Analyze and trade off PLL topology specifications
Requirements:
• Master’s degree or PhD in Electrical Engineering
• 5+ years of PLL design and...