Advance FPGA technology with Altera as a Synthesis Engineer in Toronto, Ontario. Contribute to optimizing RTL designs and enhancing synthesis processes on cutting-edge FPGA platforms.

Altera is seeking an experienced FPGA Development Tools Engineer for its Synthesis team. This role requires at least 6 years of expertise in FPGA/ASIC design and strong skills in RTL synthesis using Verilog, SystemVerilog, or VHDL. You will significantly impact the quality of results by improving synthesis algorithms and their integration across toolchains.

Key Responsibilities:
• Design and implement synthesis algorithms for RTL conversion
• Enhance the FPGA compiler flow with tight integration
• Optimize performance, power, and area using synthesis-driven techniques
• Develop tools for analyzing complex RTL designs
• Debug synthesis results and drive resolution of issues

Requirements:
• 6+ years of experience in FPGA or EDA tools...