About the Position

In this role you will use SystemVerilog and UVM methodologies, working from specifications to deliver coverage‑closed, verified, and debugged FPGA designs.

You will be responsible for developing verification environments and leveraging third‑party VIP as appropriate.

You will verify FPGA‑based designs, blocks, and sub‑systems within complex systems, working closely with design teams.

You will be part of a strong and experienced engineering team, contributing to high‑performance FPGA development projects.

Key Responsibilities

• Perform design verification of FPGA‑based systems integrating custom logic and third‑party IP blocks
• Develop and maintain verification environments using SystemVerilog and UVM methodologies
• Create and execute test plans, testbenches, and test cases
• Debug simulation issues and identify root causes
• Coll...