As a Microelectronics Digital Designer at CELERA, you will work full‐time in Lisbon or Porto, contributing to the architecture, design, verification, and integration of digital blocks for power‐management ICs and mixed‐signal PMICs.

You will translate system‐level requirements into digital specifications, state machines, and control algorithms, develop synthesizable RTL (Verilog/SystemVerilog), and collaborate closely with analog, product, and verification teams to ensure successful silicon.

Daily activities include:

• Designing low‐power digital blocks optimized for area, leakage, and dynamic consumption
• Developing UVM‐based verification environments, testbenches, assertions, and coverage models
• Running mixed‐signal co‐simulation with Verilog‐AMS, SPICE, and behavioral analog models
• Supporting silicon bring‐up, debug, and characterization
• Work on synthesis, timing closure, floorplanning, and UPF power intent