Chipright is looking for Physical design engineers who are experts in the full digital IC design flow and specifically in floorplanning, the complete Place and Route flow, Signoff Static Timing Analysis, Timing closure activities and physical verification.
The scope of work includes the physical implementation of blocks in TSMC 7nm process, specifically, the following aspects of the physical flow:
Create clock constraints & perform block level clock tree synthesis
Ownership of block level timing closure activities
Floorplanning of the blocks
Complete place & route of the blocks
Physical verification of the blocks
Signoff STA of the blocks
Creation of all necessary design views for integration into toplevel
Implementation of top-level signoff driven ECOs
Contribute to top-level design closure and signoff
Perform and ensure clean signoff checks for timing, physical verification, multi-voltage, formal & IRDROP for all agreed blocks
Organize regular revi...