About the role

As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape‑outs and work closely with system teams for chip bring‑up and validation.

Qualifications

• BS/MS degree in Electrical Engineering or Computer Science.
• 10+ years of relevant ASIC design experience.
• Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
• Proficiency in Verilog/SystemVerilog RTL design.
• Experience in high-speed Serdes design and familiar with Ethernet (802.3) standards.
• Knowledge of synthesis and static timing analysis.
• Experience developing testbenches and test cases; familiarity with UVM.
• Experience with gate-level simulations, chip bring‑up, and validati...