Lead the verification efforts at Synopsys as a Principal Engineer, focusing on UVM and SystemVerilog expertise. Innovate in memory interface IP testing and enhance product quality.
In this pivotal role, you will be responsible for developing and implementing verification strategies that improve performance and thoroughness in complex digital systems. Your analytical skills and attention to detail will drive the creation of comprehensive functional coverage models that guarantee product success. Collaborate with cross-functional teams to refine verification processes and tackle challenging debugging scenarios.
Key Responsibilities:
• Design and create comprehensive functional coverage models
• Collaborate on verification strategies with cross-functional teams
• Implement UVM-based verification environments
• Solve complex verification bugs with advanced techniques
• Mentor junior engineers and cultivate team knowledge
Requirements:
• Expertise in UVM and Syste...