Be part of Ciena's next-generation solutions as a Senior ASIC Engineer focusing on synthesis and timing analysis. This role enhances your engineering career within a people-first culture.
As part of Ciena's tech team, you'll be responsible for executing frontend ASIC implementation and validating complex designs. Your role will involve significant interaction with multidisciplinary teams, ensuring high-quality integration of the Wavelogic DSP programs. The position promises collaboration and continuous growth in a supportive environment.
Key Responsibilities:
• Implement frontend designs for assigned ASIC subsystems
• Validate clock domains for top-level integration
• Optimize and document synthesis workflows
• Execute logical equivalence verification for designs
• Work closely with ASIC integration and physical design teams
Requirements:
• B.Sc. in Electrical or Computer Engineering or equivalent
• Proficient in ASIC synthesis and timing analysis tools