The Senior ASIC Physical Design Engineer will be responsible for executing end-to-end digital physical design activities—from RTL or netlist input through final GDSII—ensuring high-quality, high-performance, and manufacturable digital blocks and subsystems. The role requires strong expertise in synthesis, floorplanning, place & route (P&R), timing closure, power integrity, extraction, verification, and tape-out preparation.

You will collaborate closely with digital/analog design and CAD/PDK teams, verification, and program management to deliver robust silicon on schedule.

Key Responsibilities

• Perform digital physical layout design including: Floorplanning, power planning, place and route, physical verification and sign-off flows, Extraction, STA, EM/IR analysis, and reliability checks.
• Perform logic synthesis meeting timing, area, and power targets, Debug and resolve timing violations through logic restructuring, Implement functional ECOs...