Elevate your career with Ciena as a Senior ASIC Synthesis Engineer. Leverage your expertise in synthesis and static timing analysis to support cutting-edge DSP programs.
Ciena is seeking a talented engineer to focus on frontend implementation in high-performance ASIC technology. You will drive innovation through synthesis, static timing analysis, and ensure logical equivalence verification for system integrity. Collaborate with cross-functional teams to optimize design workflows and maintain high-quality deliverables within project timelines.
Key Responsibilities:
• Execute frontend implementation and synthesis for ASIC subsystems
• Develop and maintain timing constraints for subsystem integration
• Perform logical equivalence checks between RTL and gate-level netlists
• Validate clock domain crossings for ASIC integration
• Create tools and documentation to enhance synthesis workflows
Requirements:
• B.Sc. in Electrical Engineering or related field
• Expe...