Job Overview

This position requires candidates to upload a resume in English; multiple versions may be submitted, but at least one English version is required to be considered for this position. We are looking for a hands‑on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. The engineer will own verification planning, UVM testbench development, test content creation (directed and constrained‐random), coverage closure, and debug across block, subsystem, and SoC levels, collaborating closely with design, architecture, firmware, and validation teams to deliver high‑quality silicon on schedule.

Key Responsibilities

Own the verification lifecycle for one or more IPs/subsystems/SoC top‑level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff.

Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models), with scalable, reus...