We are seeking a hands‑on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. The role includes ownership of verification planning, UVM testbench development, test content creation, coverage closure, and debugging across block, subsystem, and SoC levels. Collaboration with design, architecture, firmware, and validation teams is essential to deliver high‑quality silicon on schedule.

• Own the verification lifecycle for one or more IPs/subsystems/SoC top‑level features: requirements decomposition, test plan definition, coverage strategy, execution, and sign‑off.
• Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models), with scalable, reusable components.
• Develop test content: constrained‑random sequences, scenario tests, stimulus libraries, checkers, and assertions.
• Debug failures quickly and methodically across simulation and emul...