Launch your career with Synopsys as a Mixed-Signal AMS Co-Simulation Verification Engineer, focusing on high-impact SERDES IP developments. Perfect for those eager to innovate in connectivity solutions.
At Synopsys, we welcome engineers who thrive at the intersection of analog and digital. This role is perfect for a proactive individual, whether a new graduate or seasoned professional, driven to ensure silicon reliability through rigorous verification processes. Your contributions will influence critical design paths in leading-edge technologies.
Key Responsibilities:
• Develop and manage detailed verification plans for SERDES
• Create UVM-based System Verilog testbenches for co-simulation
• Validate functionality across SERDES TX/RX paths and algorithms
• Troubleshoot and debug across analog and digital interactions
• Execute design assessments ensuring silicon durability
Requirements:
• Degree in electrical engineering or related field
• Strong grasp of ...